Gate Side Injection Operating Mode for 3D NAND Flash Memories

In this paper, we investigate a new operating mode for 3D-NAND flash cell programming and erasing. Whereas conventional flash cells are operated by injecting charges from the channel, this new scheme relies on charge injection from the gate electrode by reversing the order of the dielectric layers in the stack. The benefits are twofold: improved ISPP slope which can exceed the theoretical limit of 1 in conventional operation, and cumulative impact of ferroelectric switching and charge trapping on the magnitude of the memory window. We optimize the gate stack towards improved programming characteristics as required for 3D-NAND scaling, while ensuring erase capability and good retention.