Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL’s and Vertical BL for Better Cell Size Scaling and Array Selection

A previously reported 3D stackable DRAM, utilizing a capacitor-less three-WL gate-controlled thyristor (GCT) with vertical BL and shared WL for cross-bar selection, encounters challenges such as limited forward break-over voltage (VFB) shift with source line bias changes and a large sector-erase unit. To address these limitations, we propose an enhanced version of GCT- based 3D DRAM. While retaining the vertical BL concept, it incorporates a distinctive feature from 3D 1T1C DRAM—the horizontal WL. This innovation allows array decoding through modulation of WL and BL bias, enabling independent adjustment of WL bias for different layers to achieve a smaller page-erase unit. Furthermore, the scaling capability of GCT is showcased by employing only two separated WL’s with different channel lengths, facilitating a reduction in cell size and an increase in cell read current.