On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation

In the last years several ultra-low voltage (ULV) operational transconductance amplifiers (OTAs) with supply voltages below 0.5V have been proposed in the literature. To achieve high gain, multi-stage amplifiers are frequently exploited, in spite of the complexity of design and compensation approaches, whereas cascode and regulated-cascode OTA topologies have rarely been exploited to implement ULV amplifiers. On the other hand, most ULV amplifiers are designed for IoT and biomedical applications in which reducing power consumption is the most important specification, and MOS devices are operated in the subthreshold region. This paper focuses on exploiting the subthreshold operating region to design ULV single-stage OTAs that utilize an output cascoded branch to increase the equivalent output resistance and, consequently, the overall voltage gain. A detailed analytical study of the conditions for triode and saturation regions for MOS devices operating in deep subthreshold region is presented to demonstrate that, for an appropriate choice of the inversion coefficient (IC), a cascode configuration exhibits higher gain than a single transistor, for the same voltage overhead, even in ULV conditions. More specifically, the results presented in this work demonstrate that 4 MOS devices (2 NMOS and 2 PMOS) can be reliably stacked to build a complementary cascode amplifier, even with a supply voltage as low as 0.4V. We also present a novel topology of regulated-cascode amplifier suitable to be operated with a supply voltage of 0.4V and a voltage gain approaching 100dB. Simulation results referring to a 180nm CMOS technology and including PVT and mismatch variations confirm state-of-the-art performances, as well as the good robustness of the proposed regulated-cascode ULV OTA.