Design of Panel Level Package and Power and Signal Integrity Analysis

This study explores the integration of Redistribution Layer (RDL) technique and Panel Level Package (PLP) technology to enhance the miniaturization and performance of electronic products focusing on the PCIe and SDRAM sections of an SSD with PM8617 as the main controller. Using Allegro PCB Designer and Ansys simulation tools, the project investigates impedance matching and crosstalk effects. Results indicate satisfactory performance for DDR4 SDRAM, with minimal attenuation and impedance variations. However, the PCIe circuit exhibits poor characteristics at high frequencies, attributed to impedance mismatches and crosstalk issues. The study emphasizes the importance of Power Integrity (PI) and Signal Integrity (SI) simulations in identifying and optimizing circuit performance. In conclusion, the research provides insights into signal transmission characteristics, identifies performance issues, and suggests improvements for advanced packaging technologies in electronic products.