Addressing Advanced IC Substrate Deformation and Pattern Distortion using an Extremely Large Exposure Field Fine-Resolution Lithography System

The process of adding multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate. Formation changes experienced by the panel, as a result of thermal, high-stress and other fan-out processes, shift the design location from its nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. And then there is the matter of tightening resolution requirements. To address these challenges, and better serve the heterogeneous integration process, an extremely large exposure field, fine-resolution lithography solution was proposed to enable packages up to
$\mathbf{250}\mathbf{mm}\times \mathbf{250}\mathbf{mm}$
without the need for image stitching, while meeting the overlay and critical dimension uniformity requirements for these packages.