Behavioral and Variability Analysis of Enclosed Layout Transistors for Radiation Hardened Analog Circuits

The enclosed layout transistor (ELT) is a layout technique aimed at reducing the sensitivity of CMOS devices to total ionizing dose effects. In this alternative layout, the gate completely surrounds the drain or source, avoiding the building of thick field oxide between these terminals, to prevent the increase of leakage current of devices working under radiation. Design of ELTs usually imposes challenges regarding asymmetry between source and drain (which impacts electrical characteristics) and calculation of effective aspect ratio (W/L). For this reason, our research group has been conducting works on design and characterization of ELTs for analog circuits. These works have led to the proposal of an alternative layout, called Pseudo-Symmetric (PS) ELT, with the intention of obtaining a better performance matching between ELTs and regular layout transistors designed with the same effective aspect ratio. In the current work, we present the performed electrical characterization of such ELT style, comparing it to traditional square ELTs, as well as to regular two-edge devices. In addition, an inter-die variability study was performed. A total of 25 samples of circuits containing asymmetric ELTs, PS-ELTs and two-edge transistors were characterized. The devices were fabricated in a 130 nm process. To access the variability and the impacts of using different types of ELTs their coefficients of variation (CV) were calculated. Gate leakage and sub-threshold currents were also compared. The experimental results point to a good agreement between the tested electrical parameters of the pseudo-symmetric ELTs and its correspondent two-edge devices. All devices presented CVs lower than 5% for all parameters analyzed in this work, indicating that using the ELT as layout method does not significantly alter the dispersion of the measured parameters.