Enhancing DAC Precision with INL and DNL Reduction via Memristor-Integrated Design

In this work, the main focus is to identify and build a compact and optimized digital-to-analog converter (DAC). The DAC is analyzed based on power consumption, area of the circuit, signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential nonlinearity (DNL), integral nonlinearity (INL) and effective number of bits (ENOB). In conventional DAC, there are some issues related to power consumption, DNL, and INL. In this research work, the objective is to build a compact memristor-based R-2R ladder DAC to reduce the limit of the DNL and INL of the output signal. 45nm CMOS technology and VTEAM memristor model are utilized for the simulation that is performed in Cadence Virtuoso. A memristor is used for its characteristics, including its low area and low threshold voltage. The introduced 4-bit DAC consumes 720 μ
$W$
at 1V supply voltage and produces a moderate value of SNR, SNDR, and SFDR ranging between 50 dB to 65 dB. However, the DNL and INL are significantly low at only 0.001 LSB.