A Comprehensive Investigation of $\text{GaSb}/\text{GaAs}_{0.5}\text{Sb}_{0.5}/\text{GaAs}$ based Double Gate Source-Pocket Engineered Heterogeneous Gate Dielectric Vertical TFET for Optimized Low-Power Applications

Recognizing the simplified fabrication and advanced performance of Vertical Tunnel Field Effect Transistors (VTFET) compared to Lateral TFET, numerous research has been con-ducted. In this study, a comparative analysis was performed on two double gate heterojunction source-pocket engineered VTFETs with and without heterogeneous cascaded gate dielectric using ATLAS SILVACO TCAD software. Highly doped
$\text{GaSb}$
as source intensifies the tunneling rate.
$\text{GaAs}_{0.5}$
Sb
0.5
as source pocket reduces lattice mismatch and increases
$\mathrm{I}_{\mathrm{o}\mathrm{n}}$
. The research indicates that using High-k and & Low-k thick gate dielectrics at source and drain ends reduces average subthreshold swing
$(\text{SS}_{\mathrm{a}\mathrm{v}\mathrm{g}})$
, enhances transcenductance
$(\mathrm{g}_{\mathrm{m}})$
, and amplifies
$\mathrm{I}_{\mathrm{o}\mathrm{n}}/\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$
ratio exponentially. This research examines Analo
$y_{\mathrm{R}\mathrm{F}}$
and DC performances of VTFET to optimize crucial device parameters. The heterogeneous gate dielectric structure incorporating
$\text{HfO}_{2}$
showed an improved
$\mathrm{I}_{\mathrm{o}\mathrm{n}}$
of
$1.1\times 10^{-5}\mathrm{A}/\mu \mathrm{m}$
, diminished leakage current
$\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$
of
$1.05\times 10^{-17}\mathrm{A}/\mu \mathrm{m}, \text{SS}_{\mathrm{a}\mathrm{v}\mathrm{g}}$
of 19.6
$\text{mV}/\text{dec}$
, highest
$\mathrm{I}_{\mathrm{o}\mathrm{n}}/\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$
ratio of
$1.04\times 10^{12}$
and
$\mathrm{g}_{\mathfrak{n}\mathrm{l}}$
of
$45\mu \mathrm{S}$
. The analysis revealed that the study is appropriate for assessing low-power applications with increased performance and also has a great potential for broadening the realm of vertical TFETs.