Design and Performance Analysis of an Asynchronous 16×2 DRAM Architecture Using 2T1C DRAM Bitcell and 70.15 µW GDI Based 2 to 4 Decoder

DRAM is a necessary component for memory-based electronics, and its use is growing constantly as engineers have been trying to meet customer requirements by making portable and low-power gadgets for the last couple of decades. One of the most significant issues is with the power dissipation of circuits which requires a lot of electricity. In this paper, to enhance the performance criteria of such systems, a novel (4×4) DRAM array has been designed using 45 nm technology in cadence tool where a different read or write path has been proposed to improve read and write abilities. Among different logic techniques, Gate-Diffusion Input (GDI) has been found to have the best performance matrices. In this regard, two 2 to 4 decoders have been constructed utilizing GDI technology which offers a propagation delay of 0.034ns, speed power product of 0.0024 pJ, and slew rate of 208.85 GV/s, to perform read or write operation in a particular location of the memory array. To evaluate, the schematic of proposed the 16×2 DRAM Architecture has been first simulated by setting up proper analog stimuli for 160 ns time frame, resulting in only 974.98 µW power dissipation. A clean physical layout of the model has also been built in accordance with the rules of Design Rule Check (DRC), Electrical Rule Check (ERC), and Layout vs. Schematic (LVS). The proposed model has also been verified by PVT corner analysis and Monte Carlo simulation to examine the uncertainty that can affect the operation and performance in temperature variation, ranging from -40°C and 125°C, in a full custom chip. Though compared to conventional DRAM cells, the suggested DRAM cell shows improved write and read margins, the designed layout has some blank space inside the PR boundary.