A 5.5 dBm 125–140 GHz ×6 Frequency Multiplier Operating With -27 dBm Input Power in 28-nm CMOS

This article presents a D-band ×6 frequency multiplier in 28-nm bulk CMOS. It consists of a balanced doubler, a differential tripler, and several amplifiers to increase conversion gain and output power. In order to generate stable output tones despite low-input power, an input amplifier with two common-source (CS) stages and a doubler with active load-based p-type MOSFET (pMOS) diode connection are implemented. As a result, the multiplier operates stably from -27 dBm input level. The measured output power and peak conversion gain are 5.5 dBm and 29.5 dB, respectively. A 15 GHz 3-dB bandwidth is measured with input power of -20 dBm. The implemented frequency multiplier consumes 107.1 mW with 0.9 V of supply voltage, and the area including pads is 0.42 mm2.