Improving the Performance Predictability of Faulty Data Caches

The aggressive reduction of the supply voltage, aiming for ultra-low power operation, affects the reliability of ICs and especially the memory structures (SRAM cells). Furthermore, the increasing usage of real-time applications into various facets of our daily lives has emphasized the necessity for predictable execution times of applications operating on these systems. In this work, we study the impact of defective first-level data caches (DL1) on system performance and its performance fluctuation. Based on analysis, we propose new fault-tolerance mechanisms that are able to mitigate the average performance degradation and at the same time, to reduce the performance deviations from the average value increasing this way the performance predictability. Our gem5-based evaluation results across a wide range of percentages of malfunctioning cells, a plethora of fault maps and the benchmarks from the Worst- Case-Execution-Time (WCET) suite show that the proposed mechanism achieves its purpose.