A Comparative Study of D-Type Flip-Flop Architecture Using 90-nm and 45-nm CMOS Technology for High-Performance and Low-Power Systems

High-performance and low-power very large-scale integration (VLSI) systems are essential performance parameters for digital electronic technologies. Flip-flops are critical components in VLSI systems because they are commonly used for data processing and storage. This paper describes the design and construction of D-type flip-flops with five transistors (DFF-F) using 90-nm complementary metal-oxide-semiconductor (CMOS) technology and D-type flip-flops with five transistors (DFF-F) using 45-nm complementary metal-oxide-semiconductor (CMOS) technology. The simulation results of the schematics, operational characteristics, and equivalent layouts of the DFF-F architecture are implemented and compared using 90-nm and 45-nm scaling technologies. Performance parameters such as chip size (layout area), average power consumption, power delay product, rise time, fall time, and propagation delay of the DFF-F architecture using two different scaling technologies are compared and analyzed with Cadence virtuoso design software. The main goals of these two strategies include lower production costs, reduced power consumption, quicker processing speeds, and smaller size.