Performance Analysis of Full Adder Using Different CMOS Technology

Very large-scale integrated (VLSI) circuits in the arithmetic logic unit depend heavily on extremely quick processing. Another crucial concern is lowering the power usage of physical tools. This paper presents a comprehensive performance analysis of full adders implemented using various CMOS technologies. The main target is evaluating key metrics such as power consumption and propagation delay. Different CMOS technologies, including 45 nm and 90 nm, are considered for the design and implementation of full-adder circuits. The number of transistors, delay time, and average power consumption in CMOS technology are significant determinants of integrated circuit performance and efficiency. The performance characteristics of these circuits are assessed through extensive simulation and analysis using Quartus II software and Cadence Virtuoso Tools. CMOS-based technology is used in this paper to achieve high speed and low power consumption.