Challenges of Semiconductor Micro Via Fabrication Technology for 3D Chiplet Interconnect

Chiplet integration technology, which has the potential to scalable expand capabilities by integrating many IC chips with different manufacturing processes, structures, and functions while maintaining the data transfer bandwidth between IC chips, is attracting attention as a promising method to solve the problems such as slowdown of Moore's law and the von Neumann bottleneck. Die-to-die bridge structures that connect dies via locally placed bridge chips with high-density interconnects is expected for scalable chiplet integration. In this paper, we propose plasma etching technologies to realize novel die-to-die bridge architecture called “Pillar-Suspended Bridge (PSB)”, and new through-silicon via etching technologies for 3D-IC integration, as well.