A Study on Cross-Level Interconnection of Metal Layers Under 193 Immersion Lithography Conditions

In advanced integrated circuit manufacturing technology, equipment, materials, and processes are continually improved to meet the requirement for smaller and more efficient chips. Lithography, a crucial step in chip manufacturing, requires continuous research and development. Metal layers, serving as the interconnect layers, usually have very complex patterns. This is because there are usually many metal and via layers, which takes a big fraction of the total manufacturing cost. Hence, If we can reduce the number of metal and via masks, the manufacturing cost may be significantly reduced. By accommodating more complex patterns in the metal layers, we may save more mask area and thereby reduce the number of masks. This paper will focus on the study of the cross-level interconnection patterns that may appear in the Back-End-Of-the-Line (BEOL) metal layers at 14 nm and 7 nm through simulation with self-developed tool based on Finite-Difference Time-Domain (FDTD) algorithm.