The Modeling and Optimization of Line Width Roughness in Polysilicon Gate for Improving the Performance of CMOS Device

The impact of line width roughness (LWR) on transistor performance is one of the hot research topics in the semiconductor industry. This paper investigates the effect of the LWR on the electrical characteristics of 55nm bulk MOSFETs using power spectral density (PSD). A method is provided for analyzing long range LWR using experimental data. It can effectively predict the impact of LWR on the performance of transistors with different gate lengths under the same process flow. By using different plasma etching mask materials, the roughness of the gate width was successfully reduced by over 1nm, and the transistor leakage was reduced by 60%.