Enhancement of Sram Read and Write Noise Margin by Device Performance Adjustment

The continuous shrinking of device size and the lower power-supplied voltage bring challenges to SRAM reading and writing stability. Compared with some methods of improving read and write stability by losing area, speed, or power consumption. Improving the standard deviation cannot only increase read and write windows but also does not reduce the device itself performance. This paper tried to reduce the reading and writing margin variation by adjusting the lightly doped drain (LDD) of NMOS. An appropriate LDD dosage can simultaneously make the read and write window 2 sigma larger than BSL in traditional 6T SRAM.