Short-Loop Method to Shorten Gate Process Characterization Cycle Time

With CMOS device scaling down, process flow becomes more and more complicated and time-consuming. To shorten learning cycle is critical for technology development. Compared with full-loop method (from beginning to end through the wafer whole process flow), short-loop method (only a few parts of process steps) has the advantages of quicker feedback on Continuous Improvement Plan (CIP) conditions, as well as less resources (cost, manpower) needed. In this paper, we demonstrate the short-loop methodology to characterize Gate process, extracting electrical parameters such as Effective Work Function (eWF), Equivalent Oxide Thickness (EOT), which have direct impact on device performance.