Study on 28NM Technology Node ILD0-CMP Micro_Scratch Defect Reduction

With the rapid development of IC (Integrated Circuit) devices, defects which come from CMP (Chemical Mechanical Planarization) process including dishing, residue and scratch have become inconvenient yield detractors. As the expansion of application scenarios, many ideas of characteristic 28nm HK (high-k) metal gate (MG) technology have been put forward, in which 28HKL+ with unique N/P work function split presents an important challenge to us. In order to optimize 28HKL+ ILD0 (Zero Inter Layer Dielectric)-CMP dishing, the hard oxide is selected as dielectric film, which is different from other 28HK products. However, the unexpected seesaw effect appeared between slight dishing and worse micro_scratch in 28HKL+ ILD0-CMP process. In this work, a novel approach has been developed to tackle this challenge, which can reduce micro_scratch ∼70% without influencing the good dishing performance. This work not only solves the yield killer and promotes the development of 28HKL+, but also provides a new perspective for solving micro_scratch in FEOL (front end of line) CMP.