A 16-Bit 8MSPS SAR ADC with a Configurable Low-Power Comparator

This paper demonstrates a 16-bit 8MSPS successive approximation register (SAR) analog-to-digital converter (ADC) with a configurable low-power comparator. Based on bottom plate sampling and bootstrap switch, this SAR ADC adopts segmented capacitive DAC arrays and a dynamic SAR control logic, with a proposed configurable comparator to lower power consumption. This proposed SAR ADC is designed and simulated in a 0.18-um BCD process, whose power consumption is reduced by 10.12% compared with the traditional structures while achieving 14.07 ENOB at 8MSPS sampling rate.