The Formation of Air Gaps Isolation Used in Metal/Dielectric Stacking

Due to miniaturization of semiconductor devices, parasitic capacitors (C
P
) in devices cause severe resistor capacitor (RC) delay. In order to reduce the C
P
of the device, we use tunable plasma enhanced Tetraethyl Orthosilicate (PETEOS) to deposite silicon oxide (SiO
X
) within the trench between metal lines of each layer to form air gap structures. Thus, the C
P
of devices can be greatly reduced and the RC delay can be optimized. Such process for forming air gap structures in metal/dielectric stacking shows great potential in reducing C
P
for future DRAM development.