A Novel FPGA-Driven HD-SPWM Architecture With Zero-Sequence Voltage Insertion Strategy for Three-Level NPC Inverter

Driven by the demand for enhanced performance and efficiency of power electronic converters, this article presents a novel architecture for the high-definition sinusoidal pulseidth modulation technique. The proposed architecture combines the two dc-linked capacitor voltages and three reference voltage signals of a three-level neutral-point clamped (NPC) inverter to effectively address the imbalances in dc-linked capacitor voltages, even during the transient conditions. By adding an offset voltage to the three-phase reference voltage, the proposed strategy achieves robust voltage balancing. A mathematically formulated voltage balancing algorithm has been developed to calculate the injected zero-sequence voltage and compensating neutral-point voltage, enabling versatile operation across a wide range of power factor angle and modulation index. The proposed approach offers several advantages, including high-resolution and high-frequency performance, reduced switching losses, higher efficiency, and minimal field-programmable gate array resource utilization. Notably, it eliminates the need for closed-loop controllers and three-phase current information, resulting in a favorable balance between functionality and design complexity. The exceptional capabilities and potential of the proposed strategy are showcased through detailed design considerations, theoretical analysis, and experimental validation on a small-scale NPC inverter prototype. Furthermore, to highlight its efficacy, a comprehensive comparative analysis has been conducted, evaluating the proposed architecture against recently-reported similar techniques.