MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements

In today’s digital security, the robust 64-bit cryptographic algorithms are key to fulfilling strict security standards. However, most existing cryptographic architectures primarily support 8/32-bit algorithms and often exhibit poor performance. Therefore, this paper proposes a multi-grained reconfigurable cryptographic accelerator (MRCA) to efficiently support a variety of 8/32/64-bit algorithms with high performance and energy efficiency. To achieve this, we propose three innovative ideas. Firstly, a dual processing element array (D-PEA) is proposed to perform either two parallel 32-bit algorithms or concatenate them for 64-bit algorithms. Secondly, we develop a synchronous row connection and processing element architecture with a double buffer lane to reduce context memory and enable flexible coordination and computation of data in both 32-bit and 64-bit algorithms. Thirdly, we propose a concatenable 32-bit crypto ALU within each processing element, which can not only execute multiple 32-bit cryptographic operations in a single cycle but also connect to support multiple 64-bit operations. Our MRCA has been successfully implemented and verified across various 8/32/64-bit cryptographic algorithms on the TySOM-3A FPGA platform. Our ASIC experiment on a 45nm CMOS technology shows that the MRCA achieves a remarkable throughput from 0.43 to 15.48 Gbps and energy efficiency ranging from 0.4 to 14.46 Gbps/W, covering a wide range of 8-bit, 32-bit, and 64-bit cryptographic algorithm computations. Compared to previous studies, the MRCA outperforms by 3.5-12 times in throughput and 3.7-20 times in energy efficiency for hashing computations, also offering enhanced flexibility in supporting a wider range of 64-bit algorithms.