p-GaN Gate HEMTs on 6-Inch Sapphire by CMOS-Compatible Process: A Promising Game Changer for Power Electronics

The ≥ 650 V power electronics market penetration by GaN HEMTs on Si has been impeded by the GaN buffer. Recently, GaN-on-sapphire, a promising solution, attracts great attentions. In this work, p-GaN gate HEMTs are successfully manufactured on 6-inch sapphire by CMOS-compatible process in our pilot line. Device process modules of p-GaN selective etching, low-temperature Ohmic contact, and Al2O3/SiO2 passivation have all be realized. The fabricated
$16~\mu $
m–
${L}_{\text {GD}}$
devices with a simplified epitaxy and device structure, feature a low
${R}_{\text {ON}}$
of
$14.8~\Omega \cdot $
mm, a high
${V}_{\text {TH}}$
of 2 V, and a high OFF-state breakdown voltage (BV) over 1360 V. Further, the nonuniformity of the
${R}_{\text {ON}}$
and
${V}_{\text {TH}}$
across the 6-inch whole wafer is well controlled. Devices also passed the preliminary reliability assessment of high temperature gate bias (HTGB) stress and high temperature reverse bias (HTRB) stress. The high-reliability, high-uniformity, and low-cost p-GaN gate HEMTs on 6-inch sapphire will probably be a strong driven force for the power electronics market in the near future.