An FPGA based Scheme for Real-Time Max/Min-Set-Selection Sorters

Partial sorting has several potential uses, one of which is choosing the M greatest or smallest numbers from N inputs. This short discussion seeks to introduce readers to a novel approach for max/min-set-selection sorters implemented in real-time utilising field-programmable gate arrays (FPGAs). Our approach is quite extensible, yet it is not directly proportional to the vector length. Using sorting networks for bitonic sequences simplifies programming, which is the main rationale behind our technique. Additionally, two variants of our method have been created to address the high data rate sequence and a multiple of two max/min-set-selection problems, respectively. In conclusion, our method's efficacy is demonstrated on a single Xilinx XC7VX690T FPGA through comparison with state-of-the-art technology.