Improved HF-FOM and SC Ruggedness of Split-Gate 4H-SiC MOSFET With P+ Buffer

In this letter, a novel Split-Gate SiC MOSFET is proposed by introducing a P+ buffer (SG-PB-MOS) into the JFET region. The P+ buffer serves to enhance device oxide reliability by mitigating the peak oxide electric field (
${E}_{\max }\text {)}$
. Besides, the P+ buffer facilitates depletion of the JFET region under high drain voltage, suppressing the short-circuit current. The SG-PB-MOS, Split-Gate MOSFET (SG-MOS), and conventional MOSFET (C-MOS) are systematically characterized through TCAD simulations. Cell-level parameter distributions are observed and analyzed to validate the efficacy of the proposed structure. In blocking states, the SG-PB-MOS demonstrates the mildest
${E}_{\max }$
. Moreover, compared to the C-MOS and SG-MOS, the SG-PB-MOS exhibits a
$1.5\times $
and
$2.1\times $
improvement in short-circuit withstand time (SCWT), a
$5.2\times $
and
$2.4\times $
improvement in high-frequency figure-of-merit (HF-FOM,
${R}_{\text {on}} \times {Q}_{\text {gd}}\text {)}$
, respectively. Notably, these enhancements are achieved with negligible impact on
${R}_{\text {on}}$
. As a result, SG-PB-MOSFET shows superior trade-offs in both
${R}_{\text {on}}$
&
${E}_{\max }$
,
${R}_{\text {on}}$
& SCWT, and
${R}_{\text {on}}$
&
${Q}_{\text {gd}}$
, making it suitable for high reliability and high power-density applications.