A 43.9 μs IRS Controller SoC With Grid-Based Phase-Shift Optimization in 28 nm CMOS Technology for Next- Generation Communication

Intelligent reflecting surface (IRS) is one of the promising technologies for next-generation communication systems. Although IRS can enhance the integrity of the transmitted signal, however, it requires additional phase-shift optimization task, potentially increasing the total processing latency of the system. To implement a phase-shift optimization algorithm with low-latency, for the world-first, IRS controller SoC for saving the base station (BS) transmit (TX) antenna power is presented with novel latency reduction techniques; 1) grid-based phase-shift elements with a coarse-grained update, 2) quality-aware approximate processing element with low-resolution saturation arithmetic, 3) optimized data-flow scheduling with double-buffer architecture, and 4) novel low-latency weight update tracking technique. By adopting the proposed techniques, the fully-optimized SoC architecture can enhance the processing latency and energy consumption by 93% and 68%, respectively, compared with the unoptimized SoC architecture. The proposed system is designed and fabricated in 28 nm CMOS technology, where the implementation results show that the fully-optimized SoC system can achieve
$43.9~\mu $
s of processing latency while saving 14.5 dB of TX antenna power for optimizing the
$16\times 16$
grid-based IRS architecture with
$128\times 8$
MU-MIMO configuration.