Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM Using HK/MG Process Technology

The effect of Off-state stress on a propagation delay (tPD) and a data-valid window (tDV) was characterized. The experimental result showed that the Vth of PMOSET reduced due to the electron trapping into the nitride in the STI, thus resulting in the decrease in tDV. The extracted time slope n of NBTI, off-state degradation,
$\Delta \text{tPD}, \Delta \text{tDV}$
were ∼0.23, ∼0.4, ∼0.32, and ∼0.4 respectively. It indicates that the degradation of tDV was dominated by the off-state stress. Thus, the mechanism of off-state degradation was investigated by varying the physical dimensions of the transistor and STI structure. Moreover, an empirical model of tDV degradation was proposed using device models such as off-state stress, NBTI, HCI, and it matched well with an experimental result measured at the system level. With this model, various processes such as implantation, SiGe channel, and STI structure were optimized, and as a result, the off-state stress is well controlled.