Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology

A new modeling framework to describe the negative bias temperature instability (NBTI) characteristics in gate-all-around (GAA) stacked nanosheet transistor is proposed. Three dimensional simulations of Si-H bond de-passivation and re-passivation, hydrogen species generation and transport, interface trap and bulk trap generation, and threshold voltage shift are examined. The extracted voltage-acceleration factor and effective activation energy are in close match with experimental data for Si channel GAA NSFETs. For further validation, the impact of nanosheet thickness, channel stress and SiGe channel on GAA NBTI characteristics are investigated using this modeling framework and the model projections are found to align very well with published reports.