Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays

The impact of Program/erase (P/E) cycling on Cell V
T
Distribution (CVD) during retention bake in 3-D NAND Charge Trap Flash (CTF) arrays is modeled. Experimental data under the Solid Pattern (SP) test is analyzed using the Activated Barrier Double Well Thermionic (ABDWT) model. Only two adjustable parameters can model the DR loss across various P/E cycles, Bake Temperature (BT), Program Level (PL), and CVD level (sigma). The relative contributions from the different underlying physical mechanisms are determined.