Layout Guidelines against Charging Damage from the Well-Side Antennas in Separated Power Domains

In this paper, we propose layout guidelines to significantly mitigate the charging damage from well-side antennas in separated power domains. We specifically focus on the circuit topologies that consist of aggressor-victim pairs. The guidelines are based on the silicon data from the test patterns that cover adequate combinations of different geometries of isolation wells, metals, and vias, as well as different well configurations. The method has been verified in 0.13µm BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer) as the isolation well.