Investigation of Positive Bias Temperature Instability in advanced FinFET nodes

PBTI in advanced FinFET nodes has been characterized and modelled by leveraging the efficient defect separation technology in this paper. Two types of traps are identified, including Type-B
e1
and Type-B
e2
,
which can be well described by incorporating the activation state into the two-state NMP theory. Type-B
e1
located in the IL layer and may originate from Vo or HB in SiO
2.
Type-B
e2
located in the HK layer but its physical origin is still unclear. The physical model of each type of traps is established and the predictive capability under DC&AC conditions, long-term reliability under low stress voltage and arbitrary waveform conditions are verified. Finally, by simplifying the physical model into a compact form and embedding it into commercial EDA software, the impact of PBTI on circuit performance is evaluated, and the safe operating voltage range of the circuit is analyzed, which provides guidance for designers to improve the reliability and life of the product.