Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress

By using the charge pumping technique to measure interface trap density, we investigate the interface degradation of 4H-SiC MOSFETs after experiencing negative threshold shift from high voltage gate stress, and after additional stress at lower voltage to raise the threshold voltage back to near its original value. The measurements show a clear increase in total interface trap density after each stress, but no change in the energy profile of traps near the band edges. The shift in flatband voltage extracted from the charge pumping data indicates a buildup of net positive oxide trapped charge density of about 3×10¹² cm⁻² after the high voltage stress. The evolution of interface trap density over time is also characterized for different voltages near the critical voltage where negative threshold shift occurs, and the results reveal insights about the mechanisms of SiC MOSFET interface degradation at high gate voltages.