Exploring the border traps near the SiO2-SiC interface using conductance measurements

The high density of interface and border traps is responsible for the reduced mobility and threshold voltage instabilities in state-of-the-art SiC power devices. In this work, we have performed high resolution conductance measurements on four 4H-SiC metal oxide semiconductor (MOS) capacitors annealed in various environments and temperatures to study the properties of these traps. The measurements are performed in a wide frequency range of 1 Hz to 10 MHz and reveal the presence of i) a shallow defect centre
$(\mathrm{P}_{01})$
with activation energy
$(\mathrm{E}_{\mathrm{A}})\leqslant 0.1\ \text{eV}$
and a capture cross section
$(\sigma_{\mathrm{c}})\leqslant 1\times 10^{-{20}}$
cm
²
, and ii) a relatively deep defect
$(\mathrm{P}_{02})$
, across all the samples after thermal oxidation. Post-oxidation annealing in NO at 1300°C leads to an increase in concentration of these two defect centres in addition to the generation of a new defect,
$\mathrm{P}_{03}. \mathrm{P}_{01}$
is assigned to the border traps that are likely present in the oxide at around 2-2.5 nm away from the
$\text{SiO}_{2}$
-SiC interface, while
$\mathrm{P}_{02}$
and
$\mathrm{P}_{03}$
are attributed to traps present at the interface.