A Systematic Study of HCI Improvement in FinFET with Source/Drain Implant and Geometry Modulation

We performed a systematic study on hot carrier injection (HCI) in I/O FinFETs using various source/drain (S/D) extension implantation and geometry modulation schemes. While previous publications focused on nMOS, we extended our investigation to pMOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. Electrical characterization and 3D TCAD simulation confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. In this paper, we summarized various strategies that can be used to optimize the process for both HCI reliability and performance of nMOS and pMOS FinFETs.