On-Chip Characterization of Random Telegraph Signal Noise in Bulk 90 nm CMOS

With the evolution of CMOS technology, it has become crucial to probe into intrinsic noise sources, particularly Random Telegraph Noise (RTN). This paper presents an on-chip architecture for characterizing RTN with statistical confidence levels relevant to modern integrated circuits (ICs) and provides results from test structures fabricated in SkyWater Technology's 90 nm bulk CMOS process. Leveraging a multi-step approach, a thorough pre-processing scan of an array of 128x96 devices provides a cursory view of parametric variability, and an exhaustive analysis provides a statistical view of RTN. This research underscores the importance of accurate RTN characterization, paving the way for efficient CMOS design strategies.