Investigation of Read Disturb for Hf0.5Zr0.502 Ferroelectric Field-Effect Transistors Based Neuromorphic Applications

In this work, the impact of read scheme together with polarization state of the ferroelectric (FE) domains on the interface trap behavior of FeFETs for NOR array applications were investigated. Hf
0.5
Zr
0.5
O
2
(HZO)-based FeFET with different interfacial layer (IL) treatments were fabricated and used for the analysis. Generally, as gate voltage
$V$
G increases, the trap energy will move closer to the Fermi energy, which increases the occurrence of trapping/de-trapping at the transistor interface. Furthermore, it is found that higher drain voltage
$V_{D}$
can help to suppress the read operation induced IL degradation, especially for devices at the low-threshold voltage
$V_{th}$
(LVT) state. Since higher
$V_{D}$
will lead to a reverse electric field between gate and drain, the FE domains near the drain junction can be negatively switched and helps to repel the electrons captured by the acceptor-like traps. An experimentally calibrated TCAD simulation was constructed and used to support the theoretical explanation. Careful design of read scheme is necessary to optimize the read disturb issues in the FeFET-based memory arrays.