An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology

The electrostatic discharge (ESD) phenomenon is a critical reliability concern, and the charged device model (CDM) is well known for its relatively high voltage peak with few nanoseconds duration on the gate oxide (GOX), resulting in breakdown. However, as ESD design window shrinks, even GOX degradation before hard breakdown during component-level CDM qualification can cause reliability issues such as soft-failures. This degradation can be attributed to the quickly increased electric field on the GOX, leading to the rapid creation of trapped charges before catastrophic damage. This study analyzes CDM-induced bias temperature instability (BTI)-like degradation and models threshold voltage (Vth) shift using a very-fast transmission line pulse (VF-TLP) with 1ns pulse width and 200ps rise and fall time, generally proposed for CDM evaluation. The experiment was conducted with various VF-TLP voltage peaks, numbers of pulsing iterations and GOX areas. And, finally, Vth shift model considering statistical variation is presented. This model can be a guideline to prevent CDM-induced GOX degradation at an early design stage.