A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead

We propose a radiation-hardened flip-flop (FF) combined with a transient-fault tolerant (TFT) structure and fabricated test chips in a 65 nm FD-SOI technology. Heavy ion irradiation tests show that the cross section of the proposed TFT FF is about two orders of magnitude lower than that of a standard FF when linear energy transfer of irradiated heavy ions is 69 MeV-cm
²
/mg. The TFT FF achieves high error tolerance with 35% area, 15% delay and 9% power overhead, and its energy-delay product is half as large as a conventional stacked FF.