A 28nm 157TOPS/W 446.9Kb/mm2 Compute-In-Memory SRAM Macro with Analog-Digital Hybrid Computing for Deep Neural Network Inference

Compute-in-memory (CIM) has achieved remarkable performance and energy efficiency for accelerating deep neural networks (DNNs). While digital CIM enables high accuracy, the adder tree has become a bottleneck in improving energy and area efficiency due to numerous adder cells and routing congestion. On the other hand, analog CIM provides high energy efficiency with a small area, albeit with lower accuracy than its digital counterpart. Charge-domain computing provides relatively high accuracy [1]–[2], but DAC consumes a large amount of energy due to the large capacitance of the capacitor array, limiting energy efficiency (Fig. 1, bottom left). Additionally, computation errors are accumulated over bitwise operations, resulting in noticeable accuracy drops at high precision (Fig. 1, top left). Recent hybrid CIM designs try to solve those issues by combining analog and digital computation [3]–[4].