A 11 pA/√Hz TIA with +15dB input OMA Range for 112Gb/s PAM4 Optical Links in 22nm FDSOI

High-speed optical links are advancing towards higher density and bandwidth (BW) to facilitate the scaling of data centers. A transimpedance amplifier (TIA) is a critical component in the optical chain that significantly affects the noise, BW, linearity, and power consumption of intensity modulated optical links. Recently, CMOS inverter-based shunt-feedback (IBSF) TIAs (Fig. 1) have proven satisfactory noise and BW performance for 100Gb/s receivers [1]–[4]. However, they do so by trading off linear dynamic range. The use of large feedback resistor (R
f
) to improve noise, compromises the linearity of the TIA at high input currents. Furthermore, most IBSF-TIAs operate from an effective 1V supply voltage [1]–[4], exacerbating this tradeoff. Nevertheless, based on IEEE specifications, it is imperative to meet bit-error-rate (BER) of 4.8E-4 with margin up to +4dBm of optical modulation amplitude (OMA). This corresponds to photodiode (PD) currents of 2.5mApp for a responsivity of 0.8 A/W. To understand the tradeoff, Fig. 1 plots the signal-to-noise-and-distortion ratio (SNDR) for three different TIA designs. Each design is optimized for a different R
f
value, and includes the full amplifier chain. At low OMA inputs, TIA is noise limited; hence the TIA with larger R
f
provides the best SNDR in that region. However, at high OMA input, where the performance is linearity limited, the TIA using smallest R
f
provides better SNDR. Nevertheless, none of the TIAs satisfy the required specifications between −6dBm to +4dBm. To extend the dynamic range, one could adjust the R
f
dynamically inside the automatic gain control (AGC) loop [5], however this approach only modulates the low frequency part of the transimpedance (Zt) and causes irreparable damage to the quality of the PAM4 eye. Alternatively, a variable optical attenuator (VOA) can be employed in the optical receiver to reduce the maximum input current. This comes at the expense of larger power consumption and/or more complexity in the AGC loop. In this work, a CMOS TIA is proposed to overcome the linearity-noise tradeoff in IBSF TIAs.