A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI

Low-jitter clock generation and frequency synthesize is essential in modern communication and computing systems. In 5G and beamforming systems, low Phase-Noise (PN) clock, for example, enhances spectrum efficiency [1]. Moreover, high-speed data converters needed for digital radio applications demand for sub 50 fs-rms sampling clocks [1], [2]. This work aims to develop a compact single-coil Phase Locked Loop (PLL) that exploits potentials of sub-sampling architecture to implement a low-power and low-jitter clock generator, achieving −258.5 dB Power-Jitter Figure of Merit (FoM) in 45nm RF SOI technology. To achieve the target performance, a reconfigurable discrete-time integrating phase detector (DTPD) has been proposed that operates at full rate (29 GHz), alleviating the need for any frequency division. The proposed low-power, high-speed, and low-noise DTPD enables the implementation of an efficient sub-sampling PLL. In addition, a VCO and a VCO-buffer pair, with matched circuit topology, are suggested to minimize power dissipation and deign complexities of this block. Performance of the proposed sub-sampling PLL has been measured at different reference clock frequencies to demonstrate the capability of the proposed DTPD to operate properly at different rates, thus progressively produce an output clock with lower PN. To alleviate the stability issues, the DTPD circuit can be switched to a double-phase structure to enhance the feedback update rate, thus offering a higher loop phase margin and lower jitter peaking.