A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode

State-of-the-art processor cores run in a wide range of states (P/C-states) spanning high performance (PO) to ultra-low power with data retention (C1), each requiring its own optimal operating voltage. Ondie low dropout regulator (LDO) architectures [1]–[5] which reuse power gating headers to enable per-core DVFS from a single global VDD (GVDD) have gained popularity due to their relative ease of integration on die. Distributed LDOs [1]–[4] driving a shared Power Delivery Network (PDN) are a scalable architecture with increasing core size and current demands and can adapt better to local load transients. However, the minimum dropout achieved in [1]–[4] is >=40mV for peak currents which limits the max achievable frequency in P0 state. This dropout happens because the PFET headers are arranged either in rows separated by >800μm [1], or in a mesh like network with separation of few 100μm between the PFET clusters [2]–[4], with the inherent resistance of the PDN (RPDN) becomes a bottleneck. [5] proposes only a top and bottom row of PFETs and uses thick package layers to minimize RPDN and can achieve dropout of -20mv. This topology is however not scalable with increasing core size, as the current must funnel in and out of the top and bottom PFET rows and we quickly approach the max current limits of vias and bumps. Dedicating package resources to route virtual VDD (VVDD) per core is another overhead. In the C1 state, core is clock-gated and needs to operate at a voltage sufficient to retain state. Regulator control overhead can negate any power savings achieved and hence a low power overhead mechanism to lower the voltage is preferred. To address these issues, this paper presents (1) A power delivery scheme comprising of finely distributed power gates for minimal dropout, a distributed linear regulator with low area overhead, and a diode-based retention mode as shown in Fig. 1, (2) a continuous time comparator for reacting to sub-ns local load transients, and (3) a metastability tolerant Delay Locking Loop (DLL) based Digital to Analog Converter (DAC) to locally generate the analog reference voltage from a globally transmitted digital code using fixed frequency reference clock.