An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS

Wide frequency coverage phase locked loops (PLL) with fine frequency resolution and low phase noise are one of the most critical building blocks for the high speed communication systems. Voltage domain quantization scheme employing ADCs has been proposed in previous fractional-N PLLs as an alternative to DTC-based quantization cancellation. However, though the voltage-domain quantization is linear in modern processes, the potential nonlinearity in the time-to-voltage conversion preceding the ADC results in fractional spurs and noise folding, which will severely degrade the PLL output if not properly addressed. One approach applies linearity compensation that often requires sophisticated digital processing [1]–[2]. The other approach utilizes digital-to-time converters (DTC) or digital-to-analog converters (DAC) to generate a replica of the divider quantization noise and then cancels out this noise in the analog domain before it propagates into the loop [3]–[4], thus relaxing the requirement for linear phase detection range. Prior arts have achieved remarkable phase noise performances, at the cost of significantly higher design complexity. This work describes a wideband fractional-N PLL that uses an integrator-based time-to-voltage converter and a 10-bit SAR ADC for direct phase error digitization as shown in Fig. 1. Without linearity calibration or DTC/DAC-based quantization noise cancellation, the proposed PLL achieves low fractional spur and low jitter across a wide frequency range.