A Pseudo-Adiabatic Switched-Capacitor Gate Driver for Si and GaN FETs Achieving >5x Power Reduction

Conventional gate drivers use resistive or current-limited charging and discharging of reactive gate energy, resulting in hard-switching power loss - an important limitation on converter efficiency [1]–[4]. Shown in Fig. 1, this work uses a fast, tunable switched-capacitor (SC) converter to step the gate voltage waveform in smaller incre-ments, reducing charge sharing losses through pseudo-adiabatic switching and recovering gate energy in flying capacitors. Using a 5-level SC driver, the design uses all low-voltage (1.2V 130nm SOI) CMOS to generate the stepped $5\mathrm{V}_{\text{pp}}$ gate waveform from a ~1Vsup-ply. By using fast control and sub-ns tunability of each switching step, the design achieves 2-7x reduction in gate drive power while still maintaining fast gate and drain voltage rise/fall times (slew rates). The SC stage timing is used to mitigate (parasitic) gate loop inductive effects, ringing, and overshoot, providing different modes of operation that allow new opportunities and tradeoffs between power savings switching transient speed.