A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering

Latest wireless communication systems desire ADCs to pursue wide-BW (160MHz) and high-DR (65dB) to support ever-increasing data transfer rates and higher-order modulation schemes. Continuous-time (CT) pipeline ADC/DSM draws growing attention as it combines the easy-to-drive and inherent anti-aliasing merits of CT operation with adequate resolution from pipeline operation, where OSR is restricted by high sampling frequency (Fs). Meanwhile, when GHz-Fs is utilized to broaden the signal BW in the CT pipeline converter, two design issues arise related to the front-end stage: 1) path delay mismatch between input signal path and quantization (QTZ) path; 2) image signal produced by switching of DAC on QTZ path, which lies on integer multiples of Fs and easily saturates the backend stage. This paper proposes a CT pipeline DSM with correlative passive RC low-pass filters (LPFs) that help alleviate the abovementioned issues. The DAC image filtering in residue amplifier (RA) is moved to the QTZ path and realized by a simple RC-LPF2, which pre-filters the DAC image before the DAC current is injected into the RA, reducing the RA's swing, slew rate, and its associated power consumption. On the other hand, another RC-LPF1 is inserted into the analog signal path to emulate the required delay that matches the operation time of the QTZ path. Benefits from the RC components correlation between RC-LPF1 and RC-LPF2, this structure avoids the usage of the LC- or tuned-RC-lattice all-pass/low-pass filter (APF/LPF) in the front-end stage [1]–[3]. For the back-end design, an APF analog delay is proposed to be inserted in the CIFF CTDSM to restore the STF=1 under the ELD effect, maintaining matching simplicity between analog and digital domains. In the CT pipeline converter system, the residue signal VRES is produced by cancellation between continuous-moving input and Fs-clocked DAC output, as shown in Fig. 1. VRES has large and sharp sawtooth edges (originated from the DAC image), which can easily saturate the RA and back-end stage and limits their performance. For pipeline ADC operations (>800MHz BW), RC/LC APF/LPF lattice delays are used in the analog signal path for delay matching, and 1^st or $2^{\text{nd}}$ order active LPF was introduced in the RA to suppress the high-frequency DAC image [1]–[3]. The usage of the active RA filtering causes the high-speed DAC current to go through the long route and shunt by the capacitor $\mathrm{C}_{\mathrm{f}}$ and the RA (Fig. 1 top), due to the negative feedback action of the RA which tries to maintain a quiet virtual ground. This current increases the wideband linearity requirement of the RA. In our work on CTDSM with a relaxed input bandwidth (160MHz), we propose pre-filtering by placing a passive RC-LPF2 on the QTZ path directly, suppressing the image DAC current from the very beginning of its source. In this way, the DAC high-speed current is shunt by the capacitor $\mathrm{C}_{2}$ of LPF2, and the DAC output signal is filtered before being sent to the RA's virtual ground. Due to the already-presence delay generated by the LPF2 in the QTZ path, we substitute the signal path's lattice delay with a passive RC-LPF1 (Fig. 1 bottom). It aligns the delay of the signal path with the QTZ path, which includes the delay of QTZ1-DAC1 and RC-LPF2. This ensures the accurate removal of the input signal component. Together with the LPF2's pre-filtering, VRES with diminished high-frequency contents and small amplitude is linearity/slew-rate friendly for subsequent RA and the back-end stage, which alleviates the parasitic load and linearity requirements on internal crucial nodes in the GHz-Fs systems [4]. Furthermore, the $\mathrm{R}_{1} \mathrm{C}_{1}$ and $\mathrm{R}_{2}\mathrm{C}_{2}$ of LPF1 and LPF2 are correlatively changing over process variation, empowering the delay mismatch compensation in the proposed architecture.