A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration

The advanced RA have effectively mitigated ADC performance degradation under process, voltage, and temperature (PVT) variations [1]–[2]. However, they still necessitate a one-time configuration to rectify inter-stage gain error (ISGE). In light of this, the calibration-free techniques targeting ISGE are developed to further reduce the cost associated with ISGE calibration [1], [3]–[5]. The correlated level shifting (CLS) based techniques enhance gain accuracy through multi-step amplifications [1]. However, the speed is limited by the large level shifting capacitor and phase constraints. Alternatively, dual-residue amplification technique has been introduced to circumvent the need for ISGE calibration [3]–[5]. Among these techniques, the single-RA scheme with two-step amplification proves effective in mitigating the RA mismatch issue observed in the two-RA scheme [3]. In contrast to the current interpolation [4], the capacitive interpolation consumes only dynamic power and exhibits superior energy efficiency [5]. Nonetheless, the capacitive interpolation scheme suffers from complexities in control behavior, which limits its performance when compared to common pipelined-SAR counterparts. This work introduces a one-way switching method, which enables an amenable logic and always constant capacitive digital-to-analog converter (CDAC) implementation in the capacitive interpolation. Additionally, a background offset calibration is presented to correct the offset of the 1st stage comparator and inter-stage offset to near zero. As a result, the calibration need of RA is removed.