Emerging Reconfigurable Logic Device Based FPGA Design and Optimization

Reconfigurable devices are gaining increasing attention as a viable alternative and supplementary solution to the prevailing CMOS technology. In this paper, we develop a more efficient Field-Programmable Gate Array (FPGA) based on the reconfigurable field-effective transistor (RFET). We use the multi-gate characteristics of RFET to redesign the key components of FPGAs, namely SRAM-controlled multiplexer (MUX) and look-up tables (LUTs). The compact structure of the proposed design requires fewer transistors and leads to reduced delay and energy dissipation of the overall FPGA system. In addition, we develop a framework to perform a large design space exploration across various device-level and system-level parameters. A series of benchmark tests show that under the optimal design, up to 70% and 50% reduction can be achieved in delay and energy-delay product (EDP), respectively, compared to the traditional CMOS counterparts.