Full Stage Delay Calculation Using Full Waveform Propagation and Standard Library CCS Model

Very-large-scale integrated (VLSI) circuits contain, nowadays, millions of transistors on a single chip. The design and verification of VLSI circuits involve several critical steps, including Delay Calculation for Static Timing Analysis. With excessive technology scaling, parasitic capacitance and resistance become more and more significant, while interconnect shapes become more complex. However, standard timing libraries are precharacterized only for capacitance as including the arbitrary RC interconnects shape in characterization would result in massive library files which are difficult to handle regarding memory and execution time. In this work, we propose a SPICE accurate driver, interconnect and receivers stage general delay calculation methodology which supports arbitrary RC interconnect shapes. We evaluate the accuracy and performance of our methodology compared to a traditional delay calculation methodology and SPICE, by using the Tau Workshop Contest Delay Calculation Tool Kit 2020 and 2021 and ASU ASAP7 7nm predictive PDK. Our methodology achieves 1.49% delay and 1.3% slew average Root Mean Square Error (RMSE) vs SPICE for pi-models and 0.84% delay and 1.24% slew RMSE vs SPICE for arbitrary RC interconnect, while being orders of magnitude faster.