Parasitic Capacitance Patterns Grid Density Binarization and Shifted Reflection Step Sequence Encoding for Dimensionality Reduction

The accurate extraction of interconnect parasitic capacitance is becoming increasingly crucial for integrated circuit design in advanced manufacturing processes. Previous method like field solver offers super high resolution but comes with significant computational time. In contrast, pattern-matching-based extraction methods deliver faster results, but less applicable with complex and nonlinear situations. In this study, we propose a novel method that can provide a more compact form for the existing density-based features for two-dimensional patterns in full-chip capacitance extraction, thereby significantly reducing feature dimensionality. Our method maps low-level features based on density grids to a high-level, lower-dimensional space by using physical manufacturing rules as prior knowledge, which reduces feature dimensions without losing essential information. Experimental results show that our proposed feature representation method offers significant accuracy and satisfactory runtime in simplifying pattern matching process, which makes it more practical and implementable for commercial EDA tool in large-scale integrated circuit parasitic capacitance extraction.